CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

20

®Copyright 2008 Cirrus Logic, Inc.

DS705PP2

Parameter

Symbol

Min

Max

Unit

Address setup before PCP_CS# and PCP_DS# low

5-

ns

Address hold time after PCP_CS# and PCP_DS# low

5-

ns

Read

Delay between PCP_DS# then PCP_CS# low or PCP_CS# then

PCP_DS# low

0-

ns

Data valid after PCP_CS# and PCP_DS# low with PCP_R/W# high

-19

ns

PCP_CS# and PCP_DS# low for read

24

-

ns

Data hold time after PCP_CS# or PCP_DS# high after read

8-

ns

Data high-Z after PCP_CS# or PCP_DS# high after read

-18

ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for

1. The system designer should be aware that the actual maximum speed of the communication port may be limited by

the firmware application. Hardware handshaking on the PCP_BSY# pin/bit should be observed to prevent

overflowing the input data buffer. AN288 CS4953xx Firmware Uses’s Manual should be consulted for the firmware

speed limitations.

30

-

ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for

next write1

30

-

ns

PCP_RW# rising to PCP_IRQ# falling

-12

ns

Write

Delay between PCP_DS# then PCP_CS# low or PCP_CS# then

PCP_DS# low

0-

ns

Data setup before PCP_CS# or PCP_DS# high

8-

ns

PCP_CS# and PCP_DS# low for write

24

-

ns

PCP_R/W# setup before PCP_CS# AND PCP_DS# low

24

-

ns

PCP_R/W# hold time after PCP_CS# or PCP_DS# high

8-

ns

Data hold after PCP_CS# or PCP_DS# high

8-

ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low with

PCP_R/W# high for next read1

30

-

ns

PCP_CS# or PCP_DS# high to PCP_CS# and PCP_DS# low for

next write1

30

-

ns

PCP_RW# rising to PCP_BSY# falling

-

2*DCLKP + 20

-

ns