ST10F168-Q3 datasheet(41/74 Pages) STMICROELECTRONICS

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ST10F168

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The minimum reset circuit of Figure 14 is not ade-

quate when the RSTIN pin is driven from the

ST10F168 itself during software or watchdog trig-

gered resets, because of the capacitor C1 that will

keep the voltage on RSTIN pin above VIL after the

end of the internal reset sequence, and thus will

triggered an asynchronous reset sequence.

Figure 14 shows an example of a reset circuit. In

this example, R1C1 external circuit is only used to

generate power-up or manual reset, and R0C0

circuit on VPP is used for power-up reset and to

exit from powerdown mode. Diode D1 creates a

wired-OR gate connection to the reset pin and

may be replaced by open-collector schmitt trigger

buffer. Diode D2 provides a faster cycle time for

repetitive power-on resets.

R2 is an optional pullup for faster recovery and

correct biasing of TTL Open Collector drivers.

Figure 14 : System Reset Circuit

RSTOUT

VPP

RSTIN

VCC

ST10F168

External Hardware

VCC

o.d.

External

Reset Source

Open Drain Inverter

VCC

ST10F168-Q3 bảng dữ liệu(PDF) 41 Page - STMicroelectronics