LS1012A datasheet(20/39 Pages) NXP

20 / 39 page

Table 2-6. FRWY-LS1012A clocks (continued)

Clock

Frequency

Destination

Device

ETH2_XTALIN,

ETH2_XTALOUT

25 MHz

Crystal clock for the SGMII

PHY2

CODEC_SYS_MCLK

25 MHz

System clock for audio

codec

8 MHz XTAL for K20

8 MHz

Crystal clock for K20

Crystal

BRDG_CLKIN_24MHz

24 MHz

Clock for SC16IS740IPW

SPI to Dual UART bridge

Oscillator

2.5 Double data rate (DDR) memory

The FRWY-LS1012A is supplied with one 16-bit, 512 MB DDR3L SDRAM memory,

running at data rates up to 1000 MT/s. The part number is D2516ECMDXGJD-U from

Kingston Technology.

Following are the characteristics of the LS1012A DDR3L memory controller:

• Up to 1.0 GT/s

• Supports 16 bit operation (no ECC support)

• Support for x8, x16 devices

• Supports 1 chip select, D1_MCS_B

The VR5100 VREF LDO (U8) takes 1.35 V supply and provides 0.675 V VREF supply

to the DDR3L memory.

The memory interface includes all the necessary termination and I/O power, and is routed

to achieve maximum performance of the memory bus.

2.6 Serializer/deserializer (SerDes)

The FRWY-LS1012A SerDes block provides three high-speed serial communication

lane, supporting two SGMII PHYs and 1 M.2 Type-E NGFF slot. See QorIQ LS1012A

Data Sheet for details about the SerDes protocols supported on the LS1012A processor.

The following table lists the components used to support the different SerDes options.

Table 2-7. FRWY-LS1012A SerDes embedded devices

Manufacturer

Part number

Description

Lane supported

Speed

Qualcomm

AR8033

• SGMII 1G PHY

1.25 Gbit/s

Qualcomm

AR8033

• SGMII 1G PHY

1.25 Gbit/s

Table continues on the next page...

Double data rate (DDR) memory

Layerscape LS1012A Freeway (FRWY-LS1012A) Board Reference Manual, Rev. 0, 04/2018

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