DSPIC30F2010 datasheet(101/204 Pages) MICROCHIP

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DS70118H-page 101

dsPIC30F2010

16.6

Software Controlled Clock

Stretching (STREN = 1)

When the STREN bit is ‘1’, the SCLREL bit may be

cleared by software to allow software to control the

clock stretching. The logic will synchronize writes to

the SCLREL bit with the SCL clock. Clearing the

SCLREL bit will not assert the SCL output until the

module detects a falling edge on the SCL output and

SCL is sampled low. If the SCLREL bit is cleared by

the user while the SCL line has been sampled low, the

SCL output will be asserted (held low). The SCL

output will remain low until the SCLREL bit is set, and

all other devices on the I2C bus have de-asserted

SCL. This ensures that a write to the SCLREL bit will

not violate the minimum high time requirement for

SCL.

If the STREN bit is ‘0’, a software write to the SCLREL

bit will be disregarded and have no effect on the

SCLREL bit.

16.7

Interrupts

The I2C module generates two interrupt flags, MI2CIF

(I2C Master Interrupt Flag) and SI2CIF (I2C Slave

Interrupt Flag). The MI2CIF interrupt flag is activated

on completion of a master message event. The SI2CIF

interrupt flag is activated on detection of a message

directed to the slave.

16.8

Slope Control

The I2C standard requires slope control on the SDA

and SCL signals for Fast Mode (400 kHz). The control

bit, DISSLW, enables the user to disable slew rate

control, if desired. It is necessary to disable the slew

rate control for 1 MHz mode.

16.9

IPMI Support

The control bit IPMIEN enables the module to support

Intelligent Peripheral Management Interface (IPMI).

When this bit is set, the module accepts and acts upon

all addresses.

16.10 General Call Address Support

The general call address can address all devices.

When this address is used, all devices should, in

theory, respond with an acknowledgement.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all 0s with R_W = 0.

The general call address is recognized when the

General

Call

Enable

(GCEN)

bit

set

(I2CCON<15> = 1). Following a Start bit detection, 8

bits are shifted into I2CRSR and the address is

compared with I2CADD, and is also compared with the

general call address which is fixed in hardware.

If a general call address match occurs, the I2CRSR is

transferred to the I2CRCV after the eighth clock, the

RBF flag is set, and on the falling edge of the ninth bit

(ACK bit), the master event interrupt flag (MI2CIF) is

set.

When the interrupt is serviced, the source for the

interrupt can be checked by reading the contents of the

I2CRCV to determine if the address was device

specific, or a general call address.

16.11 I2C Master Support

As a Master device, six operations are supported.

• Assert a Start condition on SDA and SCL.

• Assert a Restart condition on SDA and SCL.

• Write to the I2CTRN register initiating

transmission of data/address.

• Generate a Stop condition on SDA and SCL.

• Configure the I2C port to receive data.

• Generate an ACK condition at the end of a

received byte of data.

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