74LVC32A

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 5 — 17 November 2011

2 of 14

NXP Semiconductors

74LVC32A

Quad 2-input OR gate

4.

Functional diagram

5.

Pinning information

5.1 Pinning

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

mna242

1A

1B

1Y

2

1

3

2A

2B

2Y

5

4

6

3A

3B

3Y

10

9

8

4A

4B

4Y

13

12

11

mna243

3

≥1

≥1

≥1

≥1

2

1

6

5

4

8

10

9

11

13

12

Fig 3.

Logic diagram for one gate

mna241

A

B

Y

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 4.

Pin configuration for SO14 and (T)SSOP14

Fig 5.

Pin configuration for DHVQFN14

32

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

001aad101

1

2

3

4

5

6

7

8

10

9

12

11

14

13

001aad102

32

Transparent top view

2Y

3A

2B

3B

2A

4Y

1Y

4A

4B

1B

GND(1)

6

9

5

10

4

11

3

12

2

13

terminal 1

index area