74LVC08A

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 7 — 19 April 2016

3 of 15

NXP Semiconductors

74LVC08A

Quad 2-input AND gate

5.2 Pin description

6.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care

7.

Limiting values

[1]

The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2]

The output voltage ratings may be exceeded if the output current ratings are observed.

[3]

For SO14 packages: above 70

C derate linearly with 8 mW/K.

For (T)SSOP14 packages: above 60

C derate linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60

C derate linearly with 4.5 mW/K.

Table 2.

Pin description

Symbol

Pin

Description

1A to 4A

1, 4, 9, 12

data input

1B to 4B

2, 5, 10, 13

data input

1Y to 4Y

3, 6, 8, 11

data output

GND

7

ground (0 V)

VCC

14

supply voltage

Table 3.

Function selection[1]

Input

Output

nA

nB

nY

LX

L

XL

L

HHH

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

0.5

+6.5

V

IIK

input clamping current

VI < 0 V

50

-

mA

VI

input voltage

[1]

0.5

+6.5

V

IOK

output clamping current

VO > VCC or VO < 0 V

-

50

mA

VO

output voltage

output HIGH or LOW-state

[2]

0.5

VCC + 0.5

V

IO

output current

VO = 0 V to VCC

-

50

mA

ICC

supply current

-

100

mA

IGND

ground current

100

-

mA

Ptot

total power dissipation

Tamb = 40 C to +125 C

[3]

-500

mW

Tstg

storage temperature

65

+150

C