74HC_HCT112

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Product data sheet

Rev. 3 — 9 August 2016

9 of 20

NXP Semiconductors

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

74HCT112

tpd

propagation

delay

nCP to nQ; see Figure 6

[2]

VCC = 4.5 V

-

21

35

-

44

-

53

ns

VCC =5V; CL =15pF

-

19

-

-

-

-

-

ns

nCP to nQ; see Figure 6

[2]

VCC = 4.5 V

-

23

40

-

50

-

60

ns

VCC =5V; CL =15pF

-

19

-

-

-

-

-

ns

nRD to nQ, nQ;

see Figure 7

VCC = 4.5 V

-

22

37

-

46

-

56

ns

VCC =5V; CL =15pF

-

19

-

-

-

-

-

ns

nSD to nQ, nQ;

see Figure 7

VCC = 4.5 V

-

18

32

-

40

-

48

ns

VCC =5V; CL =15pF

-

15

-

-

-

-

-

ns

tt

transition

time

nQ, nQ; see Figure 6

[3]

VCC = 4.5 V

-

7

15

-

19

-

22

ns

tW

pulse width

nCP HIGH or LOW;

see Figure 6

VCC = 4.5 V

16

8

-

20

-

24

-

ns

nSD, nRD LOW;

see Figure 7

VCC = 4.5 V

18

10

-

23

-

27

-

ns

trec

recovery time nRD to nCP; see Figure 7

VCC = 4.5 V

20

11

-

25

-

30

-

ns

nSD to nCP; see Figure 7

VCC = 4.5 V

20

8-

25

-

30

-

ns

tsu

set-up time

nJ and nK to nCP;

see Figure 6

VCC = 4.5 V

16

7

-

20

-

24

-

ns

th

hold time

nJ and nK to nCP;

see Figure 6

VCC = 4.5 V

0

7-

0

-

0

-

ns

fmax

maximum

frequency

nCP; see Figure 6

VCC = 4.5 V

30

64

-

24

-

20

-

MHz

VCC =5V; CL =15pF

-

70

-

-

-

-

-

MHz

Table 7.

Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8.

Symbol Parameter

Conditions

25

C

40 C to +85 C

40 C to +125 C Unit

Min Typ[1] Max

Min

Max

Min

Max