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TSZ22111

• 15 • 001

BU21180FS

TSZ02201-0L5L0F300930-1-2

06.Aug.2018 Rev.002

Block Diagram

LOGIC

AVDD

C/V Converter , A/D Converter

DVDD

・

・

・

CS0

CS19

Analog Controller

LDO28

LDO15

Power On Reset

MPU

Instruction

Memory

Work

Memory

HOST I/F

OSC

Timing

Generator

TEST1

SDA,SCL

ADDR

VDD

VSS

INTB

BUS

TEST

TEST2

Timer

RSTB

・

・

・

dummy

VDD

WDT

Figure 6. Block Diagram

Description of Block

MUX, Driver, C/V Converter, A/D Converter

This block converts from capacitance to voltage and the voltage to digital value for each sensor.

LDO28

This block is AVDD LDO that supplies 2.8V to MUX, Driver, C/V Converter and A/D Converter. Referred to as AVDD in

this document.

LDO15

This block is DVDD LDO that supplies 1.5V to OSC and LOGIC. Referred to as DVDD in this document.

OSC

This block is ring oscillator for MPU and LOGIC.

MPU

This block detects ON / OFF / Long Press of switches and performs automatic calibration based on the detection results.

The result is informed by the INTB pin.

Instruction Memory

This block is Program ROM for MPU.

Work Memory

This block is Working RAM for MPU.

HOST I/F

2-wire serial bus interface compatible with I2C protocol.

Analog Controller

This block is control sequencer for MUX, Driver, C/V Converter and A/D Converter.

WDT

This block is watchdog timer reset. When the MPU is hang-upped, the system is reset by WDT.

Timing Generator, Timer

This block generates clock for MPU peripherals based on OSC clock.