651S DATASHEET

2

©2026 Renesas Electronics Corporation

August 14, 2026

Pin Assignment

Pin Descriptions

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be

connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may

be used on each clock output if the trace is longer than 1 inch.

1

2

3

ICLK

4

Q1

Q2

VDD

Q3

GND

Q4

8

7

6

5

OE

8 Pi n ( 150 mi l ) SOI C

1

2

3

ICLK

4

Q1

Q2

VDD

Q3

GND

Q4

8

7

6

5

OE

8-pin DFN

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

ICLK

Input

Clock input. Internal pull-up resistor.

2

Q1

Output

Clock output 1.

3

Q2

Output

Clock output 2.

4

Q3

Output

Clock output 3.

5

Q4

Output

Clock output 4.

6

GND

Power

Connect to ground.

7

VDD

Power

Connect +1.8V, +2.5V or +3.3V.

8

OE

Input

Output Enable. Tri-states outputs when low. Internal pull-up resistor.