SR176 datasheet(11/35 Pages) STMICROELECTRONICS

11 / 35 page

SR176

Data transfer

11/35

3.9

Transmission frame

Between the Request and the Answer data transfer, there is a guard time without ASK and

BPSK modulation, for a minimum period of t0 =128/fS. This delay allows the reader to switch

from transmission to reception mode, and is applied after each frame. After t0, the

13.56 MHz carrier frequency is modulated by the SR176 at 847.5 kHz for a period of

t1 = 128/fS, to allow the reader to synchronize. After t1, the first phase transition generated

by the SR176 represent the start bit (‘0’) of the Answer SOF. After the falling edge of the

Answer EOF, the reader has to wait for the minimum delay, t2, before sending a new

Request Frame to the SR176.

Figure 10.

Example of a complete transmission frame

3.10

CRC

The 16-bit CRC that is used by the SR176 follows the ISO 14443 Type B recommendation.

For further information, see Appendix A. The initial register content is all ones: FFFFh.

A two-byte CRC is appended to each Request and each Answer, within each frame, before

the EOF. The CRC is calculated on all the Bytes after the SOF, up to the CRC field.

On reception of a Request from a reader, the SR176 verifies that the CRC value is valid. If it

is invalid, it discards the frame and does not answer the reader.

On reception of an Answer from the SR176, it is recommended that the reader verify that the

CRC value is valid. If it is invalid, that choice of actions that are to be performed are the

responsibility of the reader designer.

The CRC is transmitted least significant byte first. Each byte is transmitted least significant

bit first.

Figure 11.

CRC transmission rules

Sent by the

Reader

Sent by the

SR176

Input Data Transfer using ASK

Sync

fS=847.5kHz

SOF

Cmd

Data

CRC

EOF

Data CRC CRC

SOF

AI09060

Output Data Transfer using 847kHz BPSK

bits

128/fS

tDR

106kb/s

CRC 16 (8 bits)

LSbit

MSbit

LSbit

MSbit

LSByte

MSByte

ai07667

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