DM9010
Single Chip Ethernet Controller with General Processor Interface
Preliminary
49
Version: DM9010-DS-P03
Apr. 28, 2005
10.3 AC Electrical Characteristics & Timing Waveforms
10.3.1 TP Interface
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tTR/F
100TX+/- Differential Rise/Fall Time
3.0
-
5.0
ns
tTM
100TX+/- Differential Rise/Fall Time
Mismatch
0
-
0.5
ns
tTDC
100TX+/- Differential Output Duty Cycle
Distortion
0
-
0.5
ns
tT/T
100TX+/- Differential Output Peak-to-Peak
Jitter
0
-
1.4
ns
XOST
100TX+/- Differential Voltage Overshoot
0
-
5
%
10.3.2 Oscillator/Crystal Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
TCKC
TCKC
39.998
40
40.002
ns
50ppm
TPWH
OSC Pulse Width High
16
20
24
ns
TPWL
OSC Pulse Width Low
16
20
24
ns
10.3.3 Processor I/O Read Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
T1
System Address(SA) valid to IOR# valid
0
ns
T2
IOR# width
10
ns
T3
IOR# valid to System Data(SD) valid
3
ns
T4
IOR# invalid to System Data(SD) bus invalid
3
ns
T5
IOR# invalid to System Address(SA) invalid
0
ns
T6
IOR# invalid to next IOR#/IOW# valid
When read DM9010 register
2
clk*
T6
IOR# invalid to next IOR#/IOW# valid
When read DM9010 memory with F0h register
4
clk*
T2+T6 IOR# invalid to next IOR#/IOW# valid
When read DM9010 memory with F2h register
1
clk*
T7
System Address(SA) valid to IO16,IO32 valid
3
ns
T8
System Address(SA) invalid to IO16, IO32 invalid
3
ns
*Note：(the default clk period is 20ns)
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