TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

22

POST OFFICE BOX 655303

APPLICATION INFORMATION

DC/DC

Converter

Regulator

Host

Power

Supply

LLC

Phy

D0 – D7

CTL0,

CTL1

LREQ

SYSCLK

D0 – D7

CTL0,

CTL1

LREQ

SYSCLK

0.1

µF

1 M

Ω

B

W

G

12 V

5 V

TPA+

TPA–

TPB+

TPB–

12 V

5 V

Isolation Boundary

Cable Shield

Terminals 7

and 8

Cable Ground

Cable Power

1394 Host Design

0.001

µF

Bus

Holder

0.1

µF

1 M

Ω

1

6

4

2

5

3

LLC

GND

Phy

GND

Bus

Holder

Figure 12. Internal Bus-Holder Isolation

The bus-holder isolation technique is cost effective and eliminates most of the components required for the

implementation of galvanic isolation described in the IEEE 1394-1995 High Performance Serial Bus Standard

in Appendix J.6. Only one 0.001-

µF capacitor per signal line is required. The principal of operation is straight

forward. When the output node switches states, the charge on the capacitor is maintained, and voltage on the

input node is pulled in the same direction as the output node. The bus holder then maintains the input state until

the output makes another transition. This allows normal input buffers to be used that do not require critical

threshold values. Critical hysteresis levels also are not required. Board area and external component cost is

reduced. Differentiation circuitry in the output buffers is not needed. High supply currents in the input buffers

are eliminated. Supply current wasted in the external bias resistors is eliminated. The propagation delay through

the single isolation capacitor is extremely small. And finally, noise margins on the input buffer is essentially the

same as for the nonisolated CMOS signal levels. Note that since no differentiation is needed the ISO terminal

on TI devices needs to be held in a high logic state (differentiation is turned off) to correctly function with

bus-holder isolation.

When higher voltage isolation is required than can be provided by the working voltage of a single capacitor, then

multiple capacitors can be implemented in series. The working voltages then increase, but the capacitance

values of each individual capacitor must be increased to maintain the same voltage for the series combination.