S2-LPSQTR datasheet(28/73 Pages) STMICROELECTRONICS

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RSSI threshold: this parameter sets the minimum signal power above which the timing recovery is started

(RSSI_TH register).

4.4.5.3.1

DLL mode

The DLL algorithm, being based on a first order loop, is only able to control the delay of the local bit-timing

generator in order to align it to the received bit period. If there is an error between the actual received bit period

and the nominal one, the relative edges will drift over time and the algorithm will periodically apply a delay

correction to recover. Since in presence of long sequences of zeroes or ones it is not possible to estimate any

timing error, the loop tends to lose lock if the period error is large (greater than 3%).

The convergence speed of the loop is controlled by the CLK_REC_P_GAIN_FAST/SLOW parameter (KP) in the

CLOCKREC1 and CLOCKREC2 registers with a smaller value yielding a faster loop. Allowed values for KP are

from 0 to 7. The optimal values obtained for all modulations and data rates are KP = 1 or KP = 2.

4.4.5.3.2

PLL mode

The PLL algorithm tracks the phase error of the local timing generator relative to received bit period and controls

both frequency and phase to achieve the timing lock. Once that the relative period error has been estimated and

corrected for example during the preamble phase, then even in presence of long sequences of zeroes or ones,

the loop is able to keep lock.

In order to improve the performance of the algorithm, two sets of gain coefficients can be configured to be used

before and after the sync word detection.

In particular, CLK_REC_I_GAIN_FAST and CLK_REC_P_GAIN_FAST are used before the SYNC while

CLK_REC_I_GAIN_SLOW and CLK_REC_P_GAIN_SLOW are used after the SYNC detection.

4.4.5.4

RX channel filter bandwidth

The bandwidth of the receiver channel filter is programmable from 1 kHz to 800 kHz. The setting goes through the

Table 37. Channel filter words

E=0

E=1

E=2

E=3

E=4

E=5

E=6

E=7

E=8

E=9

M=0

800.1

450.9

224.7

112.3

56.1

28.0

14.0

7.0

3.5

1.8

M=1

795.1

425.9

212.4

106.2

53.0

26.5

13.3

6.6

3.3

1.7

M=2

768.4

403.2

201.1

100.5

50.2

25.1

12.6

6.3

3.1

1.6

M=3

736.8

380.8

190.0

95.0

47.4

23.7

11.9

5.9

3.0

1.5

M=4

705.1

362.1

180.7

90.3

45.1

22.6

11.3

5.6

2.8

1.4

M=5

670.9

341.7

170.6

85.3

42.6

21.3

10.6

5.3

2.7

1.3

M=6

642.3

325.4

162.4

81.2

40.6

20.3

10.1

5.1

2.5

1.3

M=7

586.7

294.5

147.1

73.5

36.7

18.4

9.2

4.6

2.3

1.2

M=8

541.4

270.3

135.0

67.5

33.7

16.9

8.4

4.2

2.1

1.1

The actual filter bandwidth for any digital clock frequency can be obtained by multiplying the values in the table

above by the factor

fdig

26000000.Thebandwidthvaluesareintendedasdouble-sided.

4.4.5.5

Intermediate frequency setting

The intermediate frequency (IF) can be tuned and be controlled by the registers IF_OFFSET_ANA and

IF_OFFSET_DIG and can be set as follows:

Intermediate frequency

fIF=fxo12∙ IF _OFFSET _ANA+100

211

=fdig12∙ IF _OFFSET _DIG+100

211

(14)

where

fXOistheXTALoscillatorfrequencyandfdigisthedigitalclockfrequency.TherecommendedIFvalueis

about 300 kHz.

S2-LPS

Digital modulator

DS13831 - Rev 1

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