9DB833

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1–3

17

9DB833

MAY 25, 2018

Revision History

Issue Date Description

Page #

6/30/2010 Released to final

5/9/2011

1. Update pin 2 pin-name and pin description from VDD to VDDR. This highlights that optimal performance

is obtained by treating VDDR as in analog pin. This is a document update only, there is no silicon change.

Various

5/24/2011

1. Corrected pin description of Pins 27/28

2. Corrected orderable part number for 9DB833AGILFT

3/13/2012

1. Added additional line to PLL Bandwidth "-3dB point in High BW Mode" conditions for industrial mode

(min1.5, typ 2.7, max 4.1 MHz)

2. Added additional line to Skew, Input to Output "Bypass Mode" conditions for industrial mode (min 2500,

max 4900 ps)

6

7/5/2012

1. Changed references of PCIe Gen3 to PCIe Gen1,2,3

2. Corrected Power Connections Table - pinout was/is correct.

1, 2

9/18/2012

Updated Byte 2, bits 1, 2, 5 and 6 per char review. Outputs can be programmed with Byte 2 to be

Stoppable or Free-Run with DIF_Stop pin, not the OE pins.

12

8/25/2015 1. Added note to Byte 2 referring to 9DB434 if FFhex is the desired default.

12

6/7/2016

1. Updated typical values in electrical tables.

2. Updated clock input electrical table to latest format.

3. Updated SMbus operating frequency to 440KHz.

4. Corrected typo in Byte 0, bit 6 defaults to 0.

Various

5/25/2018 1. Updated the minimum input slew rate from 1 V/ns to 0.6V/ns.

6