MCP14E6-ESLASHMF datasheet(10/28 Pages) MICROCHIP

10 / 28 page

MCP14E6/7/8

DS20005006B-page 10

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3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1

Enable A (ENB_A)

The ENB_A pin is the enable control for Output A. This

enable pin is internally pulled up to VDD for active-high

operation and can be left floating for standard opera-

tion. When the ENB_A pin is pulled below the enable

pin, Low Level Input Voltage (VEN_L), Output A will be

in the OFF state, regardless of the input pin state.

3.2

Control Inputs A and B (IN A; IN B)

The MOSFET driver inputs are a high-impedance

TTL/CMOS compatible input. The inputs also have

hysteresis between the high and low input levels,

allowing them to be driven from slow rising and falling

signals, and to provide noise immunity.

3.3

Ground (GND)

Ground is the device return pin. The ground pin should

have a low-impedance connection to the bias supply

source return. High peak currents will flow out the

ground pin when the capacitive load is being

discharged.

3.4

Outputs A and B (OUT A; OUT B)

Outputs, A and B, are CMOS push-pull outputs that are

capable of sourcing and sinking 2.0A of peak current

(VDD = 18V). The low output impedance ensures the

gate of the MOSFET will stay in the intended state,

even during large transients.

3.5

Supply Input (VDD)

VDD is the bias supply input for the MOSFET driver and

has a voltage range of 4.5V to 18V. This input must be

decoupled to ground with a local ceramic capacitor.

This bypass capacitor provides a localized low-

impedance path for the peak currents that are provided

to the load.

3.6

Enable B (ENB_B)

The ENB_B pin is the enable control for Output B. This

enable pin is internally pulled up to VDD for active-high

operation, and can be left floating for standard opera-

tion. When the ENB_B pin is pulled below the enable

pin, Low-Level Input Voltage (VEN_L), Output B will be

in the OFF state, regardless of the input pin state.

3.7

Exposed Metal Pad (EP)

The exposed metal pad of the DFN package is not

internally connected to any potential. Therefore, this

pad can be connected to a ground plane, or other cop-

per plane on a printed circuit board, to aid in heat

removal from the package.

TABLE 3-1:

PIN FUNCTION TABLE

PDIP, SOIC,

6x5 DFN

Symbol

Description

MCP14E6

MCP14E7

MCP14E8

ENB_A

Output A Enable

IN AIN AIN A

Input A

GND

Ground

IN BIN BIN B

Input B

5OUT B

OUT B

Output B

6VDD

VDD

Supply Input

7OUT A

OUT A

Output A

ENB_B

Output B Enable

Exposed Metal Pad (DFN package only). Exposed pad is

electrically isolated.

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