PCF8534A datasheet(8/41 Pages) NXP

8 / 41 page

PCF8534A_0

Product data sheet

Rev. 00.90 — 4 February 2008

8 of 41

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

All of the display configurations given in Table 4 can be implemented in the typical system

shown in Figure 4.

The host microprocessor / microcontroller maintains the 2-line I2C-bus communication

channel with the PCF8534A. The internal oscillator is selected by connecting pin OSC

to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are

generated internally. The only other connections required to complete the system are the

power supplies (VDD, VSS and VLCD) and the LCD panel selected for the application.

7.1 Power-on reset

At power on the PCF8534A resets to a starting condition as follows:

1. All backplane outputs are set to VLCD.

2. All segment outputs are set to VLCD.

3. The drive mode ‘1 : 4 multiplex with 1

⁄3 bias’ is selected.

4. Blinking is switched off.

5. Input and output bank selectors are reset.

6. The I2C-bus interface is initialized.

7. The data pointer and the subaddress counter are cleared.

8. Display disabled.

Table 4.

Selection of display configurations

Number of

7 segment numeric

14 segment numeric

Dot matrix

Backplanes

Segments

Digits

Indicator

symbols

Characters

Indicator

symbols

240

240 (4

× 60)

180

180 (3

× 60)

120

120 (2

× 60)

160

60 (1

× 60)

Fig 4.

Typical system configuration

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

2CB

SDA

SCL

OSC

60 segment drives

4 backplanes

LCD PANEL

(up to 240

elements)

PCF8534A

SA0

VDD

VSS

VDD

VLCD

MGL744_04

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