S5D9 datasheet(39/115 Pages) RENESAS

39 / 115 page

R01DS0303EU0140 Rev.1.40

Page 39 of 115

Oct. 31, 2023

S5D9 Datasheet

2. Electrical Characteristics

Note 1.

FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.

Note 2.

See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3.

When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Note 1.

Programming or erasing the flash memory is disabled in low-speed mode.

Note 2.

See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3.

When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

Note 1.

Programming or erasing the flash memory is disable in Subosc-speed mode.

Note 2.

See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB, PCLKC,

PCLKD, FCLK, and BCLK frequencies.

Note 3.

The ADC12 cannot be used.

2.3.2

Clock Timing

Table 2.11

Operation frequency value in low-speed mode

Parameter

Symbol

Min

Typ

Max

Unit

Operation frequency

System clock (ICLK)*2

MHz

Peripheral module clock (PCLKA)*2

Peripheral module clock (PCLKB)*2

Peripheral module clock (PCLKC)*2,*3

-*3

-1

Peripheral module clock (PCLKD)*2

Flash interface clock (FCLK)*1, *2

External bus clock (BCLK)

EBCLK pin output

Table 2.12

Operation frequency value in Subosc-speed mode

Parameter

Symbol

Min

Typ

Max

Unit

Operation frequency

System clock (ICLK)*2

27.8

37.7

kHz

Peripheral module clock (PCLKA)*2

37.7

Peripheral module clock (PCLKB)*2

37.7

Peripheral module clock (PCLKC)*2,*3

37.7

Peripheral module clock (PCLKD)*2

37.7

Flash interface clock (FCLK)*1, *2

27.8

37.7

External bus clock (BCLK)*2

37.7

EBCLK pin output

37.7

Table 2.13

Clock timing except for sub-clock oscillator (1 of 2)

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

EBCLK pin output cycle time

tBcyc

16.6

Figure 2.7

EBCLK pin output high pulse width

tCH

3.3

EBCLK pin output low pulse width

tCL

3.3

EBCLK pin output rise time

tCr

5.0

EBCLK pin output fall time

tCf

5.0

SDCLK pin output cycle time

tSDcyc

8.33

SDCLK pin output high pulse width

tCH

1.0

SDCLK pin output low pulse width

tCL

1.0

SDCLK pin output rise time

tCr

3.0

SDCLK pin output fall time

tCf

3.0

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