RZSLASHT2ME datasheet(109/116 Pages) RENESAS

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Table 2.47

Debug interface timing (2 of 2)

Parameter

Symbol

Min.

Max.

Unit

Reference

figure

TDI setup time

tTDIS

—

Figure 2.97

Output load:

30 pF

TDI hold time

tTDIH

—

TMS/SWDIO setup time

tTMSS

—

TMS/SWDIO hold time

tTMSH

—

SWDIO delay time

tSWDO

—

TDO delay time

With an ICE connected

tTDOD

—

For use in BSCAN

—

Capture register setup time

tCAPTS

—

Figure 2.98

Capture register hold time

tCAPTH

—

Update register delay time

tUPDATED

—

Trace clock cycle

tTCYC

—

Figure 2.99

Output load:

15 pF

Trace data delay time

tTDT

-1.5

4.0

Note 1. This value is the minimum cycle time for the normal operation of internal circuits.

The actual cycle time should be determined in consideration of the TCK capture edge timing and cable length of the connected ICE.

tTCKcyc

tTCKH

tTCKL

TCK

VIH

VIL

1/2 VCC33

VIH

Figure 2.96

TCK input timing

tSWDO

tTDOD

SWDIO (output)

TDO

tTMSS

tTMSH

TMS/SWDIO (input)

tTDIS

tTDIH

TDI

tTCKcyc

TCK

Figure 2.97

Data transfer timing

RZ/T2ME Datasheet

2. Electrical Characteristics

R01DS0441EJ0110 Rev.1.10

Mar 13, 2026

Page 109 of 116

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