RZSLASHT2ME datasheet(44/116 Pages) RENESAS

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Table 2.14

IO setting (DRCTLm register setting) condition (2 of 2)

Module

Signal

IO type

Voltage

DRCTLm register

DRVn

SRn

SMTn

GPT

(n = 0 to 17)

(m = 0, 1)

GTIOCnA, GTIOCnB

Type A

3.3 V

Middle

Slow

Disable

Type B

3.3 V

Low

Slow

Disable

GTADSMLm, GTADSMPm

—

3.3 V

Low

Slow

Disable

SCI, SPI

All signals

—

3.3 V

High

Fast

Disable

xSPI

(n = 0, 1; m = 0, 1)

XSPIn_CKP, XSPIn_CKN, XSPIn_IO[7:0],

XSPIn_CSm#, XSPIn_DS

—

1.8 V

High

Fast

Disable

—

3.3 V

High

Fast

Enable

Other than the above

—

Low

Slow

Disable

Ethernet Interface

(n = 0 to 2)

ETHn_TXCLK, ETHn_TXD[3:0]

—

1.8 V/3.3 V High

Fast

Disable

ETHn_TXER

—

3.3 V

Middle

Fast

—

ETHn_RXCLK, ETHn_RXD[3:0]

—

1.8 V/3.3 V —

—

Disable

ETHn_RXER, ETHn_COL, ETHn_CRS

—

3.3 V

—

Disable

ETHn_REFCLK, RMIIn_REFCLK

—

3.3 V

High

Fast

—

Other than the above

—

Low

Slow

Disable

Debug Interface

TRACECLK, TRACECTL, TRACEDATA[7:0],

TDO, TMS

—

3.3 V

High

Fast

Disable

Other than the above

—

Low

Slow

Disable

Other than the above

—

Low

Slow

Disable

2.5.1

Clock Timing

2.5.1.1

CKIO Pin Output Timing

Table 2.15

CKIO pin output timing

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

CKIO pin output cycle time

tCKcyc

Figure 2.2

—

53.4

CKIO pin output high level pulse width tCKH

tCKcyc / 2 − tCKr

—

CKIO pin output low level pulse width

tCKL

tCKcyc / 2 − tCKf

—

CKIO pin output rising time 1

tCKr

CKIO: High drive output

Setting

—

3.8

CKIO pin output falling time 1

tCKf

—

3.8

CKIO pin output rising time 2

tCKr

CKIO: Normal output

setting

—

CKIO pin output falling time 2

tCKf

—

CKIO pin output

tCKcyc

1/2 VCC33

tCKH

tCKL

tCKf

tCKr

VOH33

VOL33

1/2 VCC33

VOL33

VOH33

Figure 2.2

CKIO pin output timing

RZ/T2ME Datasheet

2. Electrical Characteristics

R01DS0441EJ0110 Rev.1.10

Mar 13, 2026

Page 44 of 116

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