R5F526TBAGFM datasheet(115/142 Pages) RENESAS

115 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 115 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

Note 1. fSCL = 1 /( tDIG_L + tDIG_H)

Note 2. tDIG_L and tDIG_H are the clock low and high periods as seen at the receiver end of the I3C bus using VIL and VIH.

Note 3. As both edges are used, the hold time must be satisfied for the respective edges, for example, tCF + 3 for falling edge clocks,

and tCR + 3 for rising edge clocks.

Note 4. Cb is the total capacitance of the bus lines.

Figure 2.72

tDIG_H and tDIG_L

Table 2.41

RI3C Timing (Push-Pull Timing Parameters for SDR)

Conditions: VCC = AVCC0 = AVCC1 = AVCC2 = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

SCL clock frequency

fSCL

0.01*1

—10

MHz

SCL clock low period

tLOW

—

Figure 2.72

tDIG_L

50*2, *3

——

SCL clock high period

tHIGH

—

tDIG_H

50*2

——

Clock in to data out for target

tSCO

—

Figure 2.73

SCL clock rise time

tCR

—

150 * 1 /fSCL

(capped at 60)

Figure 2.72

SCL clock fall time

tCF

—

150 * 1 /fSCL

(capped at 60)

SDA signal data hold in

push-pull mode

Controller

tHD_PP

tCR + 3*3, tCF + 3*3

—

Figure 2.74

Target

tHD_PP

—

Figure 2.75

SDA signal data setup in push-pull mode

tSU_PP

—

Figure 2.73,

Figure 2.74

Clock after repeated start (Sr)

tCASr

tCASmin/2

—

N/A

Figure 2.76

Clock before repeated start (Sr)

tCBSr

tCASmin/2

—

N/A

Figure 2.76

Capacitive load per bus line (SDA/SCL)

Cb*4

—

0.7 × VCC

0.3 × VCC

tCR

tCF

tHIGH

tDIG_H

tLOW

tDIG_L

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