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WM8959 bảng dữ liệu(PDF) 111 Page - Wolfson Microelectronics plc

tên linh kiện WM8959
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WM8959 bảng dữ liệu(HTML) 111 Page - Wolfson Microelectronics plc

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Pre-Production
WM8959
w
PP, May 2008, Rev 3.1
111
The required settings for this example are:
•
MCLK_DIV = 10b
•
PRESCALE = 0b
•
PLL_ENA = 1
•
SDM = 1
•
PLLN = 8 = 8h
•
PLLK = 0.192 = 3126h
EXAMPLE PLL SETTINGS
Table 65 provides example PLL settings for generating common SYSCLK frequencies from a variety
of MCLK reference frequencies.
MCLK
(MHZ)
SYSCLK
(MHZ)
MCLKDIV
F2
= SYSCLK *
4 * MCLKDIV
PRESCALE
F1
= MCLK/
PRESCALE
R
= F2/F1
N
K
12
11.2896
2
90.3168
1
12
7.5264
7h
86C2h
12
12.288
2
98.304
1
12
8.192
8h
3126h
13
11.2896
2
90.3168
1
13
6.947446
6h
F28Bh
13
12.288
2
98.304
1
13
7.561846
7h
8FD5h
14.4
11.2896
2
90.3168
1
14.4
6.272
6h
45A1h
14.4
12.288
2
98.304
1
14.4
6.826667
6h
D3A0h
19.2
11.2896
2
90.3168
2
9.6
9.408
9h
6872h
19.2
12.288
2
98.304
2
9.6
10.24
Ah
3D70h
19.68
11.2896
2
90.3168
2
9.84
9.178537
9h
2DB4h
19.68
12.288
2
98.304
2
9.84
9.990243
9h
FD80h
19.8
11.2896
2
90.3168
2
9.9
9.122909
9h
1F76h
19.8
12.288
2
98.304
2
9.9
9.929697
9h
EE00h
24
11.2896
2
90.3168
2
12
7.5264
7h
86C2h
24
12.288
2
98.304
2
12
8.192
8h
3126h
26
11.2896
2
90.3168
2
13
6.947446
6h
F28Bh
26
12.288
2
98.304
2
13
7.561846
7h
8FD5h
27
11.2896
2
90.3168
2
13.5
6.690133
6h
B0ACh
27
12.288
2
98.304
2
13.5
7.281778
7h
4822h
Table 65 PLL Frequency Examples



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