RZSLASHA3M datasheet(3/53 Pages) RENESAS

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RZ/A3M Group Datasheet

Section 1. Overview

R01DS0482EJ0110

Rev.1.10

Page 3 of 53

Mar 31, 2025

1.1.2

CPU Peripheral

Item

Description

Clock Pulse Generator

(CPG)

● Generates the clocks from external clock (EXCLK 24 MHz).

Maximum Arm Cortex-A55 clock: 1.0 GHz

Maximum DDR clock: 800 MHz (DDR3L-1600)

Maximum DRW clock: 200 MHz

Maximum AXI-bus clock: 200 MHz

Maximum APB-bus clock: 100 MHz

● SSC (Spread Spectrum Clock) supported

Direct Memory Access Controller

(DMAC)

● 2 modules, 16 channels per module

● Transfer request: On-chip peripheral request / auto request (software trigger)

● A specific DMA transfer interval can be specified to adjust the bus occupancy.

● LINK mode (DMA transfer under descriptor control) supported

● Transfer information can be automatically reloaded

Interrupt Controller

● Arm® CoreLink™ Generic Interrupt Controller (GIC-600) for Arm Cortex-A55

● External Interrupt pins (NMI, IRQ7 to IRQ0, TINT31-0)

● On-chip peripheral Interrupts: Priority level set for each module

General-purpose I/O (GPIO)

● General-purpose I/O ports

Thermal Sensor Unit (TSU)

● 1 channel

1.1.3

Internal Memory

Item

Description

On-chip RAM

● RAM of 128 Kbytes (ECC)

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