R7KA8M2AFECHC datasheet(71/295 Pages) RENESAS

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Table 2.24

Current of high-speed mode, CPU Sleep mode (DCDC mode)

Parameter

Symbol

Typ

Max

Unit

Test conditions

95 °C

105 °C

125 °C

Supply

current

*1*3*4

CPUCLK0 = 1

GHz

CPUCLK1 = 250

MHz

VSCR_1

ICC_DCDC*5

200

—

VCC_DCDC = 3.3 V

IDD*2

513

—

CPUCLK0 = 800

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*5

—

228

—

IDD*2

—

586

—

CPUCLK0 = 600

MHz

CPUCLK1 = 200

MHz

VSCR_1

ICC_DCDC*5

—

279

IDD*2

—

716

CPUCLK0 = 600

MHz

CPUCLK1 = 150

MHz

VSCR_2

ICC_DCDC*5

185

219

264

IDD*2

484

573

690

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. IDD depends on f (ICLK) as follows.

IDD Typ. = 0.02 × fCPUCLK0 + 0.06 × fICLK + 57 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 95℃) = 0.02 × fCPUCLK0 + 0.01 × fICLK + 477 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 105℃) = 0.02 × fCPUCLK0 + 0.01 × fICLK + 553 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_1, 125℃) = 0.02 × fCPUCLK0 + 0.01 × fICLK + 709 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 95℃) = 0.02 × fCPUCLK0 + 0.01 × fICLK + 464 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 105℃) = 0.02 × fCPUCLK0 + 0.01 × fICLK + 537 (unit : mA, fCPUCLK0 and fICLK are MHz)

IDD Max.(VSCR_2, 125℃) = 0.02 × fCPUCLK0 + 0.01 × fICLK + 691 (unit : mA, fCPUCLK0 and fICLK are MHz)

Note 3. Supply of the clock signal to peripherals is stopped in this state. This does not include the BGO operation.

Note 4. MRICLK, MRPCLK, ICLK, PCLKA, PCLKB, PCLKC, PCLKD, PCLKE and BCLK are set to divided by 64.

Note 5. Typical DCDC efficiency and the voltage of the test conditions are applied.

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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