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2.3.14
SSIE Timing
Table 2.74
SSIE timing
(1) High drive output is selected with the Port Drive Capability bit in the PmnPFS register.
(2) Use pins that have a letter appended to their names, for instance “_A”, “_B” or “_C” to indicate group membership. For the SSIE interface,
the AC portion of the electrical characteristics is measured for each group.
Parameter
Symbol
VCC
Min.
Max.
Unit
Comments
SSIBCK
Cycle
Master
tO
2.70V or above
80
—
ns
Figure 2.102
1.62V or above
80
—
Slave
tI
2.70V or above
80
—
ns
1.62V or above
80
—
High level/ low
level
Master
tHC/tLC
2.70V or above
0.35
—
tO
1.62V or above
0.35
—
Slave
2.70V or above
0.35
—
tI
1.62V or above
0.35
—
Rising time/
falling time
Master
tRC/tFC
2.70V or above
—
0.15
tO / tI
1.62V or above
—
0.15
Slave
2.70V or above
—
0.15
tO / tI
1.62V or above
—
0.15
SSILRCK/
SSIFS,
SSITXD0,
SSIRXD0,
SSIDATA1
Input set up
time
Master
tSR
2.70V or above
12
—
ns
Figure 2.104,
Figure 2.105
1.62V or above
20
—
Slave
2.70V or above
12
—
ns
1.62V or above
12
—
Input hold time
Master
tHR
2.70V or above
8
—
ns
1.62V or above
8
—
Slave
2.70V or above
15
—
ns
1.62V or above
15
—
Output delay
time
Master
tDTR
2.70V or above
−10
5
ns
1.62V or above
−10
7
Slave
2.70V or above
0
20
ns
1.62V or above
0
25
Output delay
time from
SSILRCK/
SSIFS change
Slave
tDTRW
2.70V or above
—
20
ns
Figure 2.106*1
1.62V or above
—
25
GTIOC2A,
AUDIO_CLK
Cycle
tEXcyc
2.70V or above
20
—
ns
Figure 2.103
1.62V or above
40
—
High level/ low level
tEXL/tEXH
2.70V or above
0.4
—
tEXcyc
1.62V or above
0.4
—
Rising time/falling time
tEXf/tEXr
2.70V or above
—
0.1*2
tEXcyc
1.62V or above
—
0.1*2
Note 1. For slave-mode transmission, SSIE has a path, through which the signal input from the SSILRCK/SSIFS pin is used to generate
transmit data, and the transmit data is logically output to the SSITXD0 or SSIDATA1 pin.
Note 2. 1μs at the longest.
RA8M2 Datasheet
2. Electrical Characteristics
R01DS0438EJ0130 Rev.1.30
Feb 27, 2026
Page 205 of 295



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