R7KA8M2AFDCAM datasheet(262/295 Pages) RENESAS

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VDD

RES pin

Internal reset signal

(Low is valid）

tCVM

Core Voltage detection

signal (Low is valid）

RSTSR3.CVMRF

Vdet_VDDL

CVM Disable signal

（

Low is enable）

Clear by

OFS2.CVMRDIS

Cleared

by user programming

Vdet_VDDH

tCVM

Cleared

by user programming

tCVMdet

tCVMOFF

VCVMH

Figure 2.144

Timing of core voltage monitor reset

2.12

Temperature Monitor Reset Characteristics

Table 2.113

Temperature monitor reset characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

High threshold temperature

Tj_detect_H

105

—

125

°C

Figure 2.145

Figure 2.146

Low threshold temperature

Tj_detect_L

-40

—

-20

°C

Note:

Temperature monitor reset is not supported in 0 to 95 °C product (product group A).

Temperature

Tj_detect_H

Internal reset signal

(Low is vaild.)

TEMPRCR.TSNEN

TEMPRCR.CMPEN

TEMPRCR.TEMPREN

tTSTBL*1

tRSTBL*2

Note 1. tTSTBL is the stabilization wait time of TSN.

Note 2. tTSTBL is the stabilization wait time of the comparator in TSN.

Figure 2.145

Timing of temperature monitor reset (High-temperature detection)

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 262 of 295

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