R7KA8M2AFDCAM datasheet(219/295 Pages) RENESAS

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2.3.20

PDMIF Timing

Table 2.84

PDMIF timing

Conditions: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

VCC

Min

Max

Unit

Test conditions

Clock period

tPsync

2.70 V or above

250

4000

Figure 2.120

1.62 V or above

500

4000

Clock high level

period

tPDCKWH

2.70 V or above

tPSYNC × 0.45

tPSYNC × 0.55

1.62 V or above

tPSYNC × 0.45

tPSYNC × 0.55

Clock low level

period

tPDCKWL

2.70 V or above

tPSYNC × 0.45

tPSYNC × 0.55

1.62 V or above

tPSYNC × 0.45

tPSYNC × 0.55

Clock rise time

tPDCKr

2.70 V or above

—

1.62 V or above

—

Clock fall time

tPDCKf

2.70 V or above

—

1.62 V or above

—

Setup time

tSU

2.70 V or above

—

Figure 2.121

Figure 2.122

1.62 V or above

—

Hold time

2.70 V or above

—

1.62 V or above

—

PDM_CLKn

tPDCKWH

tPDCKWL

TPSYNC

Figure 2.120

Timing of clock output (PDM_CLKn)

PDM_CLKn

(Output)

tSU

PDM_DATAn

(Input)

Figure 2.121

Receive Timing (Synchronized with the rise of PDM_CLKn)

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 219 of 295

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