R7KA8M2AFDCAM datasheet(158/295 Pages) RENESAS

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Table 2.60

SCI timing (Simple SPI) (3 of 3)

Condition 1: VCC/VCC2 = 2.70 V or above

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

Condition 2: VCC/VCC2 = 1.62 V or above

Following pins have high-speed high-drive output selected in the Port Drive Capability bit in the PmnPFS register: SCK1_A, SCK1_C,

SCK3_A, SCK4_A, SCK4_B, SCK4_C and SCK6_B

Other pins have high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC=VCC2.

Parameter

High

Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

Slave access time

—

2.70 V or above

tSA

—

3 ×

tTcyc +

Figure 2.72,

Figure 2.73

1.62 V or above

—

3 ×

tTcyc +

Slave output release time

—

2.70 V or above

tREL

—

3 ×

tTcyc +

1.62 V or above

—

3 ×

tTcyc +

Note:

tTcyc: TCLK cycle.

Note 1. Must use pins that have a letter appended to their name, for instance _A, _B, _C, to indicate group membership. SCI0, SCI1, SCI2,

SCI3 and SCI9 are instance _A, SCI4 and SCI5 are instance _B, SCI6, SCI7 and SCI8 are instance _C.

Note 2. All pins of group membership can be used.

Note 3. 1 µs at the longest

Table 2.61

SCI timing (Clock synchronous mode) (1 of 2)

Condition 1: VCC/VCC2 = 2.70 V or above

High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

Condition 2: VCC/VCC2 = 1.62 V or above

Following pins have high-speed high-drive output selected in the Port Drive Capability bit in the PmnPFS register: SCK1_A, SCK1_C,

SCK3_A, SCK4_A, SCK4_B, SCK4_C and SCK6_B

Other pins have high drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If SCI pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC=VCC2.

Parameter

High

Speed/

Default

VCC/VCC2

Symbol

Min

Max

Unit

Note

SCK clock cycle

output

Master

—

2.70 V or above

tScyc

2 (TCLK ≤ 120MHz)

4 (TCLK >

120MHz)

—

tTcyc

1.62 V or above

2 (TCLK ≤ 60MHz)

4 (TCLK ≤ 120MHz)

8 (TCLK >

120MHz)

—

SCK clock cycle

input

Slave

—

2.70 V or above

—

1.62 V or above

2 (TCLK ≤ 100MHz)

4 (TCLK >

100MHz)

—

SCK clock high

pulse width

Master

—

1.62 V or above

tSCKWH

0.4

0.6

tScyc

Slave

1.62 V or above

SCK clock low

pulse width

Master

—

1.62 V or above

tSCKWL

0.4

0.6

tScyc

Slave

1.62 V or above

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 158 of 295

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