R7KA8M2AFDCAM datasheet(146/295 Pages) RENESAS

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A16 to A00

(RFS)

SDCLK

SDCS

AP*1

DQMn

DQ31 to DQ00

RAS

CAS

CKE

(Hi-Z)

tCKED

(High)

tCASD

tRASD tRASD

tRASD

t CSD2

t AD2

(RFA)

(RFX)

(RFA)

t AD2

t CSD2

tRASD

tRASD tRASD tRASD

tCASD

tCASD tCASD tCASD

tCKED

SDRAM command

t DQMD

Figure 2.51

SDRAM self-refresh timing

2.3.7

I/O Ports, POEG, GPT, AGT, ULPT and ADC Trigger Timing

Table 2.57

I/O ports, POEG, GPT, AGT, ULPT and ADC trigger timing (1 of 4)

GPT32 Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

If GPT pins are specified across the VCC I/O and VCC2 I/O, characteristics below is guaranteed only when VCC = VCC2.

AGT Conditions:

Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

I/O ports

Input data pulse width

tPRW

5.5

—

tIcyc

Figure 2.52

EXCIN input frequency

tEXCIN

—

kHz

RTCICn (n = 0 to 2) input pulse width

tRTCICW

13.89

—

μs

Figure 2.53

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

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