R7KA8M2AFDCAM datasheet(134/295 Pages) RENESAS

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Table 2.56

Bus timing (3 of 3)

Condition 1: When using the CS area controller (CSC).

VCC = VCC_DCDC = VBATT = 1.62 V to 3.6 V, VCC2 = 1.62 V to 3.63 V

BCLK = 8 to 120 MHz, BCLKA = 8 to 120 MHz, EBCLK = 8 to 60 MHz (When VCC = VCC_USB = VBATT = 2.70 to 3.63 V)

BCLK = BCLKA = 8 to 60 MHz, EBCLK = 8 to 30 MHz (When VCC = VCC_USB = VBATT = 1.62 to 3.63 V)

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 2: When using the SDRAM area controller (SDRAMC).

BCLK = SDCLK = 8 to 125 MHz, BCLKA = SDCLK = 8 to 133 MHz

VCC = VCC_DCDC = VBATT = 3.0 to 3.63 V, VCC2 = 1.62 V to 3.63V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

SDCLK: High-speed high drive output is selected in the port drive capability bit in the PmnPFS register.

Others: High drive output is selected in the port drive capability bit in the PmnPFS register.

Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously.

BCLK = SDCLK = 8 to 66 MHz, BCLKA = SDCLK = 8 to 66 MHz

VCC = VCC_DCDC = VBATT = 3.0 to 3.63 V, VCC2 = 1.62 V to 3.63V

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF

EBCLK/SDCLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Condition

VCC/VCC2

Symbol

Min

Max

Unit

Test conditions

Address delay 2

(SDRAM)

Condition 2

3.0 V or above

tAD2

0.8

6.0

Figure 2.45 to Figure

2.51

Condition 3

3.0 V or above

0.8

CS delay 2

(SDRAM)

Condition 2

3.0 V or above

tCSD2

0.8

6.0

Condition 3

3.0 V or above

0.8

DQM delay

(SDRAM)

Condition 2

3.0 V or above

tDQMD

0.8

6.0

Condition 3

3.0 V or above

0.8

CKE delay (SDRAM) Condition 2

3.0 V or above

tCKED

0.8

6.0

Condition 3

3.0 V or above

0.8

Read data setup

time 2 (SDRAM)

Condition 2

3.0 V or above

tRDS2

2.1

—

Condition 3

3.0 V or above

6.1

—

Read data hold time

2 (SDRAM)

Condition 2

3.0 V or above

tRDH2

1.5

—

Condition 3

3.0 V or above

1.5

—

Write data delay 2

(SDRAM)

Condition 2

3.0 V or above

tWDD2

—

6.0

Condition 3

3.0 V or above

—

Write data hold time

2 (SDRAM)

Condition 2

3.0 V or above

tWDH2

0.8

—

Condition 3

3.0 V or above

0.8

—

WE delay (SDRAM)

Condition 2

3.0 V or above

tWED

0.8

6.0

Condition 3

3.0 V or above

0.8

RAS delay (SDRAM) Condition 2

3.0 V or above

tRASD

0.8

6.0

Condition 3

3.0 V or above

0.8

CAS delay (SDRAM) Condition 2

3.0 V or above

tCASD

0.8

6.0

Condition 3

3.0 V or above

0.8

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 134 of 295

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