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R7KA8M2AFDCAM bảng dữ liệu(HTML) 287 Page - Renesas Technology Corp |
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287 / 295 page  Table A3.1 Peripheral base address (4 of 4) Description Name of secure registers Base address of secure registers in secure alias region Name of non-secure registers Base address of non-secure registers in non- secure alias region Port 0 Control Registers PORT0 0x4040_0000 PORT0_NS 0x5040_0000 Port 1 Control Registers PORT1 0x4040_0020 PORT1_NS 0x5040_0020 Port 2 Control Registers PORT2 0x4040_0040 PORT2_NS 0x5040_0040 Port 3 Control Registers PORT3 0x4040_0060 PORT3_NS 0x5040_0060 Port 4 Control Registers PORT4 0x4040_0080 PORT4_NS 0x5040_0080 Port 5 Control Registers PORT5 0x4040_00A0 PORT5_NS 0x5040_00A0 Port 6 Control Registers PORT6 0x4040_00C0 PORT6_NS 0x5040_00C0 Port 7 Control Registers PORT7 0x4040_00E0 PORT7_NS 0x5040_00E0 Port 8 Control Registers PORT8 0x4040_0100 PORT8_NS 0x5040_0100 Port 9 Control Registers PORT9 0x4040_0120 PORT9_NS 0x5040_0120 Port A Control Registers PORTA 0x4040_0140 PORTA_NS 0x5040_0140 Port B Control Registers PORTB 0x4040_0160 PORTB_NS 0x5040_0160 Port C Control Registers PORTC 0x4040_0180 PORTC_NS 0x5040_0180 Port D Control Registers PORTD 0x4040_01A0 PORTD_NS 0x5040_01A0 Port E Control Registers PORTE 0x4040_01C0 PORTE_NS 0x5040_01C0 Port F Control Registers PORTF 0x4040_01E0 PORTF_NS 0x5040_01E0 Port G Control Registers PORTG 0x4040_0200 PORTG_NS 0x5040_0200 Pmn Pin Function Control Register PFS 0x4040_0800 PFS_NS 0x5040_0800 Note: Name = Peripheral name Description = Peripheral functionality Base address = Lowest reserved address or address used by the peripheral 3.2 Access Cycles This section provides access cycle information for the I/O registers described in this manual. ● Registers are grouped by associated module. ● The number of access cycles indicates the number of cycles based on the specified reference clock. ● In the internal I/O area, reserved addresses that are not allocated to registers must not be accessed, otherwise operations cannot be guaranteed. ● The number of I/O access cycles depends on bus cycles of the internal peripheral bus, divided clock synchronization cycles, and wait cycles of each module. Divided clock synchronization cycles differ depending on the frequency ratio between ICLK and PCLK. ● When the frequency of ICLK is equal to that of PCLK, the number of divided clock synchronization cycles is always constant. ● When the frequency of ICLK is greater than that of PCLK, at least 1 PCLK cycle is added to the number of divided clock synchronization cycles. ● The number of write access cycles indicates the number of cycles obtained by non-bufferable write access. Note: This applies to the number of cycles when access from the CPU does not conflict with the instruction fetching to the external memory or bus access from other bus masters such as DTC or DMAC. RA8M2 Datasheet Appendix 3. I/O Registers R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 287 of 295 |
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