R7KA8M2ADECAC datasheet(173/295 Pages) RENESAS

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2.3.11

OSPI Timing

Table 2.64

OSPI timing (1 of 9)

Conditions:

High-speed high drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_n_SCLK,

OM_n_SCLKN, OM_n_SIO7-0, OM_n_DQS.

Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: OM_n_CS0, OM_n_CS1.

Load capacitance C = 15pF

Item

Symbol

VCC/VCC2 VDD

Min

Max

Unit

Note

Cycle time

SDR without

OM_DQS

tPERIOD

2.70 V or

above

VSCR_1,

voltage

range 1

16.67

—

Figure 2.83

VSCR_2,

voltage

range 2

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

20.00

—

VSCR_2,

voltage

range 2

SDR with

OM_DQS/DDR

tPERIOD

2.70 V or

above

VSCR_1,

voltage

range 1

6.00

—

VSCR_2,

voltage

range 2

7.50

—

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

VSCR_2,

voltage

range 2

Clock output slew rate

tSRck

2.70 V or

above

VSCR_1,

voltage

range 1

0.94

—

V/ns

Figure 2.83

VSCR_2,

voltage

range 2

0.75

—

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

VSCR_2,

voltage

range 2

Clock Duty cycle-distortion

tCKDCD

2.70 V or

above

VSCR_1,

voltage

range 1

0.3

Figure 2.83

VSCR_2,

voltage

range 2

0.375

1.62 V to

2.00 V

VSCR_1,

voltage

range 1

VSCR_2,

voltage

range 2

RA8M2 Datasheet

2. Electrical Characteristics

R01DS0438EJ0130 Rev.1.30

Feb 27, 2026

Page 173 of 295

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