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132 / 295 page  2.3.6 Bus Timing Table 2.56 Bus timing (1 of 3) Condition 1: When using the CS area controller (CSC). VCC = VCC_DCDC = VBATT = 1.62 V to 3.6 V, VCC2 = 1.62 V to 3.63 V BCLK = 8 to 120 MHz, BCLKA = 8 to 120 MHz, EBCLK = 8 to 60 MHz (When VCC = VCC_USB = VBATT = 2.70 to 3.63 V) BCLK = BCLKA = 8 to 60 MHz, EBCLK = 8 to 30 MHz (When VCC = VCC_USB = VBATT = 1.62 to 3.63 V) Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF EBCLK: High drive output is selected in the port drive capability bit in the PmnPFS register. Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register. Condition 2: When using the SDRAM area controller (SDRAMC). BCLK = SDCLK = 8 to 125 MHz, BCLKA = SDCLK = 8 to 133 MHz VCC = VCC_DCDC = VBATT = 3.0 to 3.63 V, VCC2 = 1.62 V to 3.63V Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF SDCLK: High-speed high drive output is selected in the port drive capability bit in the PmnPFS register. Others: High drive output is selected in the port drive capability bit in the PmnPFS register. Condition 3: When using the SDRAM area controller (SDRAMC) and CS area controller (CSC) simultaneously. BCLK = SDCLK = 8 to 66 MHz, BCLKA = SDCLK = 8 to 66 MHz VCC = VCC_DCDC = VBATT = 3.0 to 3.63 V, VCC2 = 1.62 V to 3.63V Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 15 pF EBCLK/SDCLK: High drive output is selected in the port drive capability bit in the PmnPFS register. Others: Middle drive output is selected in the port drive capability bit in the PmnPFS register. Parameter Condition VCC/VCC2 Symbol Min Max Unit Test conditions Address delay Condition1 2.70 V or above tAD 1.0 12.5 ns Figure 2.38 to Figure 2.44 1.62 V or above 1.0 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns Byte control delay Condition1 2.70 V or above tBCD 1.0 12.5 ns 1.62 V or above 1.0 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns CS delay Condition1 2.70 V or above tCSD 1.0 12.5 ns 1.62 V or above 1.0 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns ALE delay time Condition1 2.70 V or above tALED 1.0 12.5 ns 1.62 V or above 1.0 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns RD delay Condition1 2.70 V or above tRSD 1.0 12.5 ns 1.62 V or above 1.0 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns Read data setup time Condition1 2.70 V or above tRDS 12.5 — ns 1.62 V or above 20.5 — ns Condition3 3.0 V or above 10.8 — ns Read data hold time Condition1 2.70 V or above tRDH 0 — ns 1.62 V or above 0 — ns Condition3 3.0 V or above 0 — ns WR/WRn delay Condition1 2.70 V or above tWRD 1.0 12.5 ns 1.62 V or above 1.0 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns Write data delay Condition1 2.70 V or above tWDD — 12.5 ns 1.62 V or above — 12.5 ns Condition3 3.0 V or above 1.0 10.8 ns RA8M2 Datasheet 2. Electrical Characteristics R01DS0438EJ0130 Rev.1.30 Feb 27, 2026 Page 132 of 295 |
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