CMV300 datasheet(17/56 Pages) AMSOSRAM

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Reference:CMV300-datasheet-v2.11

CMV300 Datasheet

Page 15 of 54

Parameter

Description

Conditions

min

typ

max

Units

∆VOC

Difference in

VOC between

complementary

output states

Steady State, RL

= 100Ω

IOS,GND

Output short

circuit current

to ground

VOUTP=VOUTN=GND

IOS,PN

Output short

circuit current

VOUTP=VOUTN

3.5 INPUT CLOCK

The input clock (CLK_IN) defines the output data rate of the CMV300. This master clock (CLK_IN) is 12 times slower than

the output date rate. The maximum data rate of the output is 480Mbps which results in a CLK_IN of 40MHz. The

minimum frequency is 10MHz for CLK_IN. Any frequency between the minimum and maximum can be applied by the

user and will result in a corresponding output data rate. The SPI register with address 83 must be programmed to the

correct frequency range when the CLK_IN frequency is changed.

3.6 FRAME RATE CALCULATION

The frame rate of the CMV300 is defined by 2 main factors.

Exposure time

Read out time

For ease of use we will assume that the exposure time is no longer than the read out time. By assuming this the frame

rate is completely defined by the read out time (because the exposure time happens in parallel with the read-out time).

The read-out time (and thus the frame rate) is defined by:

Output clock speed: max 480Mbps

Number of lines read-out

Number of outputs used: max 4 LVDS outputs (2 on the top and 2 on the bottom) or one parallel CMOS output

This means that if any of the parameters above is changed, it will have an impact on the frame rate of the CMV300. In

normal operation (4 outputs @ 480Mbps, 12 bit and full resolution) this will result in 480 fps.

Total readout time is composed of two parts: FOT (frame overhead time) + image readout time.

�� = (

# ��

��58

) ∗ 325 ∗ ��_��

With clk_per being the period of CLK_IN. The FOT consists of a time where the pixels are prepared for read out:

(

��58

) ∗ 325 ∗ ��_��

And an idle time until read out starts, depending on the used channels:

(

# ��

) ∗ 325 ∗ ��_��

With clk_per being equal to one period of CLK_IN and reg58 should be a multiple of 4. The FOT consists of the actual

FOT (where the control channel FOT bit is ‘1’) and 2 (using 4 outputs) or 4 (using 2 or 1 outputs) line times where the

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