DIO60120

Version 1.3, Aug 2025

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© 2025 Dioo Microcircuits Co., Ltd. Jiangsu

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10.Layout Design

The layout design of the DIO60120 regulator is relatively simple. For the best efficiency and minimum noise

problems, place four components close to the IC: CIN, L1, R1, and R2.

(1) Maximize the PCB copper area connected to the GND pin to achieve the best thermal and noise

performance. If the board space allows, a ground plane is highly desirable.

(2) Place CIN close to pins IN and GND. Minimize the loop area formed by CIN and GND.

(3) Minimize the PCB copper area associated with SW pin to avoid the potential noise problem.

(4) Avoid placing the components R1 and R2 and the trace connected to the FB pin adjacent to the SW net on

the PCB layout to prevent the noise problem.

(5) If the system chip interfaced with the EN pin has a high impedance state at shutdown mode and the IN pin

is connected directly to a power source such as a Li-Ion battery, it is desirable to add a pull-down 1 MΩ resistor

between the EN and GND pins to prevent the noise from falsely turning on the regulator at shutdown mode.