RA4M1 datasheet(61/131 Pages) RENESAS

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R01DS0355EJ0110 Rev.1.10

Page 61 of 131

Sep 29, 2023

RA4M1 Group

2. Electrical Characteristics

2.3.3

Reset Timing

Note 1.

When OFS1.LVDAS = 0.

Note 2.

When OFS1.LVDAS = 1.

Figure 2.32

Reset input timing at power-on

Figure 2.33

Reset input timing

Table 2.23

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

Figure 2.32

Other than above

tRESW

μs

Figure 2.33

Wait time after RES cancellation

(at power-on)

LVD0: enable*1

tRESWT

0.7

-ms

Figure 2.32

LVD0: disable*2

0.3

Wait time after RES cancellation

(during powered-on state)

LVD0: enable*1

tRESWT2

0.5

-ms

Figure 2.33

LVD0: disable*2

0.05

Internal reset cancellation time (Watchdog

timer reset, SRAM parity error reset,

SRAM ECC error reset, Bus master MPU

error reset, Bus slave MPU error reset,

Stack pointer error reset, Software reset)

LVD0: enable*1

tRESWT3

0.6

-ms

LVD0: disable*2

0.15

VCC

RES

tRESWP

Internal reset

tRESWT

RES

Internal reset

tRESWT2

tRESW

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