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ISO7231ADWR bảng dữ liệu(PDF) 7 Page - Texas Instruments

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ISO7231ADWR bảng dữ liệu(HTML) 7 Page - Texas Instruments

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ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V
(1) OPERATION
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
ISO7230A
ISO7231A
www.ti.com ........................................................................................................................................................................................................ SLLS906 – MAY 2008
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent
0.5
1
VI = VCC or 0 V, all channels, no load,
ISO7230A
mA
EN2 at 3 V
1 Mbps
1
2
ICC1
Quiescent
4.5
7
VI = VCC or 0 V, all channels, no load,
ISO7231A
mA
EN1 at 3 V, EN2 at 3 V
1 Mbps
4.5
7
Quiescent
9
15
VI = VCC or 0 V, all channels, no load,
ISO7230A
mA
EN2 at 3 V
1 Mbps
9.5
15
ICC2
Quiescent
8
12
VI = VCC or 0 V, all channels, no load,
ISO7231A
mA
EN1 at 3 V, EN2 at 3 V
1 Mbps
8
12
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at VCC, single channel
0
µA
IOH = –4 mA, See Figure 1
VCC – 0.4
VOH
High-level output voltage
V
IOH = –20 µA, See Figure 1
VCC – 0.1
IOL = 4 mA, See Figure 1
0.4
VOL
Low-level output voltage
V
IOL = 20 µA, See Figure 1
0.1
VI(HYS)
Input voltage hysteresis
150
mV
IIH
High-level input current
10
IN from 0 V or VCC
µA
IIL
Low-level input current
–10
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
25
50
kV/
µs
(1)
For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
Propagation delay
45
110
ISO723xA
See Figure 1
ns
PWD
Pulse-width distortion(1) |tPHL – tPLH|
12
tsk(o)
Channel-to-channel output skew (2)
ISO723xA
0
3
ns
tr
Output signal rise time
2
See Figure 1
ns
tf
Output signal fall time
2
tPHZ
Propagation delay, high-level-to-high-impedance output
15
20
tPZH
Propagation delay, high-impedance-to-high-level output
15
20
See Figure 2
ns
tPLZ
Propagation delay, low-level-to-high-impedance output
15
20
tPZL
Propagation delay, high-impedance-to-low-level output
15
20
tfs
Failsafe output delay time from input power loss
See Figure 3
18
µs
(1)
Also referred to as pulse skew.
(2)
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): ISO7230A ISO7231A



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