M68AW512D datasheet(14/18 Pages) STMICROELECTRONICS

tên linh kiện	M68AW512D

Giải thích chi tiết về linh kiện	8 Mbit 512K x16 3.0V Asynchronous SRAM

PDF	18 Pages

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

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M68AW512D

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Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms

Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms

Table 9. Low VCC Data Retention Characteristics

Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V.

2. Tested initially and after any design or process that may affect these parameters.

tAVAV is Read cycle time.

3. No input may exceed VCC +0.2V.

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

ICCDR

(1)

Supply Current (Data Retention)

VCC = 1.5V, E1 ≥ VCC –0.2V or

≤ 0.2V or UB = LB ≥ VCC –0.2V,

f = 0

510

µA

tCDR

(1,2)

Chip Deselected to Data

Retention Time

0ns

(2)

Operation Recovery Time

tAVAV

VDR

(1)

Supply Voltage (Data Retention)

≥ VCC –0.2V or E2 ≤ 0.2V or

UB = LB

≥ VCC –0.2V, f = 0

1.5

AI05985

DATA RETENTION MODE

3.6V

tCDR

VCC

2.7V

VDR > 1.5V

E1 or UB/LB

≥ VDR – 0.2V or UB = LB ≥ VDR – 0.2V

AI05986B

DATA RETENTION MODE

3.6V

tCDR

VCC

2.7V

VDR > 1.5V

E2 < 0.2V

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