LXT9782 datasheet(21/78 Pages) INTEL

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Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782

Datasheet

The LXT97x2 provides an individual serial MII (SMII) for each network port. The SMII ports

provide for communication between the Media Access Controllers (MACs) and the network ports.

The SMII bit stuffing protocol is automatically set once the network port operating conditions have

been determined

2.2

Interface Descriptions

2.2.1

10/100 Network Interface

The LXT97x2 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100

Mbps Ethernet over fiber media (100BASE-FX). Each network interface port consists of four

external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and

fiber. Refer to Table 2 on page 14 for specific pin assignments.

The LXT97x2 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX PECL

output. When not transmitting data, the LXT97x2 generates 802.3-compliant link pulses or idle

code. Input signals are decoded either as a 100BASE-TX, 100-BASE-FX, or 10BASE-T input,

depending on the mode selected. The interface speed is determined by auto-negotiation/parallel

detection or manual control.

2.2.1.1

Twisted-Pair Interface

When operating at 100 Mbps, the LXT97x2 continuously transmits and receives MLT3 symbols.

When not transmitting data, the LXT97x2 generates “IDLE” symbols.

During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being

exchanged, the line is left in an idle state.

Figure 5. LXT97x2 Interfaces

LXT97x2

RXDn

TXDn

SYNC

REFCLK

SMII

DATA

I/F

MDDIS

MDC

MDINT

MDIO

Mgmt

I/F

LEDS_n

LED/CFGn_n

VCC

LEDLATCH

LEDCLK

H/W Config

Mgmt I/F &

Port LEDs

ADD<4:0>

QSTAT

QCLK

Quick

Status

I/F

TPFOPn

TPFONn

TPFIPn

TPFINn

Network

I/F

RBIAS

22.1k

VCCIO

+3.3V

VCCD

+3.3V

GNDD

.01uF

Serial LED

I/F

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