AM2431BSDGHIALVR. datasheet(142/282 Pages) TI2

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6.11.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:

• MCU_SYSCLKOUT0

– MCU_SYSCLKOUT0 is the MCU domain system clock (MCU_SYSCK0) divided-by-4. This clock output is

provided for test and debug purposes only.

• MCU_OBSCLK0

– Observation clock output for test and debug purposes only.

• SYSCLKOUT0

– SYSCLKOUT0 is the MAIN domain system clock (MAIN_SYSCLK0) divided-by-4. This clock output is

provided for test and debug purposes only.

• CLKOUT0

– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL0_HSDIV4_CLKOUT) divided-by-5 or divided-

by-10. This clock output was provided to source to the external PHY. When configured to operate as

the RMII Clock source (50MHz) the signal must also be routed back to the RMII_REF_CLK pin for proper

device operation.

• OBSCLK0

– Observation clock output for test and debug purposes only.

• GPMC_FCLK_MUX

– GPMC_FCLK_MUX is the GPMC0 functional clock (GPMC_FCLK). This clock is provided as an

alternative GPMC interface clock when attached devices require a continuous running clock.

For more information, see Clock Outputs section in Clocking chapter and GPMC Clock Configuration section in

Peripherals chapter in the device TRM.

6.11.4.3 PLLs

Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from

off-chip power-sources.

There is one PLL in the MCU domain:

• MCU_PLL0 (MCU PLL)

There are six PLLs in the MAIN domain:

• MAIN_PLL0 (MAIN PLL)

• MAIN_PLL1 (PER0 PLL)

• MAIN_PLL2 (PER1 PLL)

• MAIN_PLL8 (ARM0 PLL)

• MAIN_PLL12 (DDR PLL)

• MAIN_PLL14 (R5F PLL)

Note

For more information, see:

• Device Configuration / Clocking / PLLs section in the device TRM.

• Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit

(PRU_ICSSG) section in the device TRM.

Note

The input reference clock (MCU_OSC0_XI / MCU_OSC0_XO) is specified and the lock time is

ensured by the PLL controller, as documented in the Device Configuration chapter in the device TRM.

AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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