AM2431BSDGHIALVR. datasheet(141/282 Pages) TI2

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Table 6-24. MCU_OSC0 LVCMOS Digital Clock Source Requirements

PARAMETER

MIN

TYP

MAX

UNIT

Fxtal

Frequency

MHz

Frequency Stability and Tolerance

Ethernet RGMII and RMII

not used

±100

ppm

Ethernet RGMII and RMII

using derived clock

±50

Duty Cycle

tR/F

Rise/Fall Time (10%-90% rise, 90%-10% fall)

4(1)

JPeriod(RMS)

Period Jitter, RMS (100k samples)

JPeriod(PK-PK) Period Jitter, Peak to Peak (100k samples)

300

JPhase(RMS)

Phase Jitter, RMS (BW 100Hz to 1MHz)

10(2)

Phase Noise(3)

100Hz

–92.3

dBc/Hz

1kHz

–112.3

10kHz

–132.3

100kHz

–142.3

1MHz

–152.3

(1)

Most LVCMOS oscillator datasheets define their maximum Output Rise/Fall times with a capacitive load much larger than the actual

load that will be applied by the combined PCB trace capacitance and MCU_OSC0_XI input capacitance. It should not be difficult to

find a LVCMOS oscillator that meets this requirement. However, the system designer must confirm the LVCMOS oscillator selected will

provide the appropriate rise/fall time to MCU_OSC0_XI input.

(2)

Most LVCMOS oscillator datasheets define their max RMS Phase Jitter using a larger bandwidth integration range than required by

this device. To get a more appropriate value, it may be necessary to contact the LVCMOS oscillator manufacture and ask them to

provide a maximum RMS Phase Jitter using the same bandwidth integration range that has been defined for this parameter.

(3)

The Phase Noise parameter is only applicable when the SerDes PHY is used for USB SuperSpeed, or PCIe operating without a

common external clock source.

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AM2434, AM2432, AM2431

SPRSP65J – APRIL 2021 – REVISED JUNE 2026

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