APM32F103C8T6 datasheet(21/78 Pages) GEEHY

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P a g e 20

Figure 6 APM32F103xB Series Clock Tree

LSICLK

40KHz

LSECLK

OSC

32.768

KHz

4-16MHz

HSECLK

8MHz

HSICLK

/128

PLLHSEPSC PLLSEL

×2.3.4

...16

PLL

AHB

Prescaler

/1,2...512

APB1

Rrescaler

/1,2,4,8,16

APB2

PRESCLAER

/1,2,4,8,16

CSS

RTC

IWDTCLK

USBDCLK

SCSEL

TMR2,3,4

if(APB1 prescaler=1)×1

else×2

TMRxCLK

(x=2,3.

USBD

Prescaler

/1,1.5,

PCLK2

TMR1CLK

TMR1

if(APB2 prescaler=1)×1

else×2

ADC

Prescaler

/2,4,6,8

ADCCLK

HCLK

PCLK1

FCLK

Cortex

System

Clock

PLLCLK

HSICLK

HSECLK

SYSCLK

MCO

RTCSEL[1:0]

SYSCLK

96MHz MAX

MCO

48MHz

96MHz MAX

48MHz MAX

FPUCLK

FPU

Prescaler

/1,2

96MHz MAX

48MHz MAX

OSC32_OUT

OSC32_IN

OSC_OUT

OSC_IN

The maximum frequency of AHB and high-speed APB of APM32F103xB series is 96MHz;

The maximum frequency of low-speed APB of APM32F103xB series is 48MHz.

4.5.2

Clock and startup

The internal 8MHz RC oscillator is used as the default clock for system startup. It can be

switched to an external 4~16MHz clock with failure monitoring through configuration; when an

external clock failure is detected, the system will automatically switch to the internal RC

oscillator. If an interrupt is set, the software can receive the corresponding interrupt.

The frequency of AHB, high-speed APB (APB2) and low-speed APB (APB1) can be configured

by prescaler. The maximum frequency of AHB and high-speed APB is 96MHz, and that of

low-speed APB is 48MHz.

For the clock tree of APM32F103xB, refer to Figure 6.

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