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Page 14
4.5.1.
Clock tree
Figure 5 Clock tree of APM32F003x4x6 series
HXT OSC
1-24MHz
LIRC
128KHz
HIRC RC
48MHz
HIRCDIV[2]
/1,3
HIRCDIV[1:0]
/1,2,4,8
CSS
IWDTCLK
WUPT
HXT clock
HIRC
HXT
LIRC
fMASTER
fCPU
/1,2,4,8,16
,32,64
HIRCDIV
Peripheral
clock
CCO
CPU
prescale
fCPU
OSC_OUT
OSC_IN
fMASTER
MCC[7:0]
Note: the counter of WUPT is not provided by fMASTER, so even if the clock of the
register has been turned off, the peripheral can continue to run.
Power management
4.6.1.
Power supply scheme
Table 5 Power supply scheme
Name
Abbreviation of name
Voltage range
Main power supply
VDD/VSS
2.4~5.5V
The VDD/VSS pin can supply power to the internal main voltage regulator (MVR)
and the internal low power voltage regulator (LPVR), and the outputs of these
two regulators together provide 1.5V power supply to the core, Flash and
SRAM.
4.6.2.
Power supply monitor
Two circuits of power-on reset (POR) and power-down reset (PDR), are



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