ST7LITE1XB datasheet(149/157 Pages) STMICROELECTRONICS

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ST7LITE1xB

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OPTION BYTES (Cont’d)

OPTION BYTE 1

OPT7 = PLLx4x8 PLL Factor selection.

0: PLLx4

1: PLLx8

OPT6 = PLLOFF PLL disable.

0: PLL enabled

1: PLL disabled (by-passed)

OPT5 = PLL32OFF 32MHz PLL disable.

0: PLL32 enabled

1: PLL32 disabled (by-passed)

OPT4 = OSC RC Oscillator selection

0: RC oscillator on

1: RC oscillator off

Notes:

– 1% RC oscillator available on ST7LITE15B and

ST7LITE19B devices only

– If the RC oscillator is selected, then to improve

clock stability and frequency accuracy, it is rec-

ommended to place a decoupling capacitor, typ-

ically 100nF, between the VDD and VSS pins as

close as possible to the ST7 device.

OPT3:2 = LVD[1:0] Low voltage detection selec-

tion

These option bits enable the LVD block with a se-

lected threshold as shown in Table 26.

Table 26. LVD Threshold Configuration

OPT1 = WDG SW Hardware or Software

Watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT0 = WDG HALT Watchdog Reset on Halt

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

Table 27. List of valid option combinations

Note 1: Configuration available on ST7LITE15B and ST7LITE19B devices only

Note: see Clock Management Block diagram in Figure 14

Configuration

LVD1 LVD0

LVD Off

Highest Voltage Threshold (

∼4.1V)

Medium Voltage Threshold (

∼3.5V)

Lowest Voltage Threshold (

∼2.8V)

Operating conditions

Option Bits

VDD range

Clock Source

PLL

Typ fCPU

OSC

PLLOFF

PLLx4x8

2.7V - 3.3V

Internal RC 1%1)

off

1MHz @3.3V

4MHz @3.3V

External clock

off

0-4MHz

4MHz

3.3V - 5.5V

Internal RC 1% 1)

off

1MHz @5V

8MHz @5V

External clock

off

0-8MHz

8 MHz

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