STPM11ATR datasheet(17/45 Pages) STMICROELECTRONICS

17 / 45 page

STPM11/12/13/14

Theory of operation

17/45

fCLK/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC

output is subtracted from the input signal. If the loop gain is high enough, the average value

of the DAC output (and therefore the bit stream) can approach that of the input signal level.

When a large number of samples are averaged, a very precise value of the analog signal is

obtained. This averaging is carried out in the DSP section which implements decimation,

integration and DC offset cancellation of the supplied

∑Δ signals. The gain of the decimation

filters is 1.004 for the voltage channel and 0.502 for the current channel. The resulting signal

has a resolution of 11bits for voltage channel and 16 bits for current channel.

7.4

Period and line voltage measurement

The period module measures the period of base frequency of voltage channel and checks if

the voltage signal frequency is in the band from fCLK/2

17 to f

CLK/2

15. An internal signal is

produced at every positive peak of the line voltage. If the counted number of pulses between

two trailing edges of this signal is higher than the fCLK/2

17 Hz equivalent pulses or if the

counting is stopped (internal signal is not available), it means that the base frequency is

lower than fCLK/2

17 Hz and an internal error flag BFR (Base Frequency Range) is set.

If the counted number of pulses within one line period is higher than the fCLK/2

15 equivalent

pulses, the base frequency exceeds the limit. In this case, such error must be repeated

three times in a row, in order to set the error flag BFR.

The BFR flag is also set if the value of the RMS voltage drops below a certain value (BFR-

on) and it is cleared when the RMS voltage goes above BFR-off threshold. The table below

shows the equivalent RMS voltage on the VIP/VIN pins according to the value of the voltage

channel calibrator.

The BFR flag is also set if the RMS voltage across VIP-VIN drops below a threshold value

calculated with the following formula:

(CT/Shunt)

Figure 15.

First order

∑Δ A/D Converter

DAC

Integrator

fCLK/4

Input analog signal

Output digital signal

∫

BFR

IRMS

⋅

−

6703

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