M50LPW080K1TG datasheet(6/44 Pages) STMICROELECTRONICS

6 / 44 page

M50LPW080

6/44

SUMMARY DESCRIPTION

The M50LPW080 is a 8 Mbit (1Mb x8) non-volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage (3.0 to 3.6V) supply. For

fast programming and fast erasing in production

lines an optional 12V power supply can be used to

reduce the programming and the erasing times.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected individually to prevent accidental Pro-

gram or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents. The end

of a program or erase operation can be detected

and any error conditions identified. The command

set required to control the memory is consistent

with JEDEC standards.

Two different bus interfaces are supported by the

memory. The primary interface is the Low Pin

Count (or LPC) Standard Interface. This has been

designed to remove the need for the ISA bus in

current PC Chipsets; the M50LPW080 acts as the

PC BIOS on the Low Pin Count bus for these PC

Chipsets.

The secondary interface, the Address/Address

Multiplexed (or A/A Mux) Interface, is designed to

be compatible with current Flash Programmers for

production line programming prior to fitting to a PC

Motherboard.

The memory is offered in TSOP40 (10 x 20mm)

and PLCC32 packages and it is supplied with all

the bits erased (set to ’1’).

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