COM200221 datasheet(21/82 Pages) SMSC

tên linh kiện	COM200221

Giải thích chi tiết về linh kiện	10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

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nhà sản xuất	SMSC [SMSC Corporation]

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10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM

Datasheet

SMSC COM20022I

Page 21

Revision 09-27-07

DATASHEET

DREQ

nWR

DMAEN bit

Writing Address

Pointer Low

minimum 4TARB

TARB is the ARBITRATION Clock Period. It depends on the TOPR and

SLOW-ARB bit. TOPR is the period of operation clock frequency (output

of the clock multiplier). It depends on the CKUP1 and CKUP0 bits.

TARB = TOPR @ SLOW-ARB = 0

TARB = 2 TOPR @ SLOW-ARB = 1

Figure 5.3 - DREQ Pin First Assertion Timing for All DMA Modes

As an example of gating by cycle, in an ISA bus system, the Refresh period is 15

μS. Continuous transfer

by DMA must be less than 15

μS to prevent blocking by the Refresh cycle. A DMA cycle of consecutive

DMA cycles is approximately 1uS. The DMA overhead time is approximately 2.5

μS. The Refresh

execution time is 500nS. This computes to 15

μS - 2.5μS - 500nS = 12μS or 12 cycles. Therefore the

DREQ pin must be negated every 12 cycles. Figure 5.4 illustrates the rough timing of the Programmable-

Burst mode DMA transfer.

COM200221 bảng dữ liệu(PDF) 21 Page - SMSC Corporation