DAC39RF10 datasheet(168/232 Pages) TI2

168 / 232 page

Table 8-58. JESD_RST Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

JESD_RST

R/W

When set, this bit holds the digital portion of the JESD circuitry in

reset but does not affect the physical lane. It may be necessary to

set this bit prior to setting JESD_EN = 1 and then clear this bit at a

later time to start processing the JESD data. This allows the supply

to settle from the large change in power that occurs when starting

the PHY and JESD clocks. This is especially important if the user

plans to use the LANE_ARR values, since these values are captured

only the first time the elastic buffer attempts to release.

8.56 EXTREF_EN Register (Offset = 02B0h) [reset = 00h]

EXTREF_EN is shown in Figure 8-57 and described in Table 8-59.

Return to the Register Summary Table.

Enable External Reference

Figure 8-57. EXTREF_EN Register

RESERVED

EXTREF_EN

R/W-00h

R/W-0b

Table 8-59. EXTREF_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

EXTREF_EN

R/W

Setting this bit enable the use of an external reference voltage on the

EXTREF ball.

CUR_2X_EN Register (Offset = 02B1h) [reset = 00h]

CUR_2X_EN is shown in Figure 8-58 and described in Table 8-60.

Return to the Register Summary Table.

DAC Current Doubler Enable

Figure 8-58. CUR_2X_EN Register

RESERVED

CUR_2X_EN

R/W-00h

R/W-0b

Table 8-60. CUR_2X_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

00h

CUR_2X_EN

R/W

Setting this bit doubles the DAC output current.

8.57 DAC_OFS_CHG_BLK Register (Offset = 02CFh) [reset = 00h]

DAC_OFS_CHG_BLK is shown in Figure 8-59 and described in Table 8-61.

Return to the Register Summary Table.

DAC Offset Adjustment Change Block

DAC39RF10-SP, DAC39RF10-SEP

DAC39RFS10-SP, DAC39RFS10-SEP

SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026

www.ti.com

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