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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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DAC39RF10 bảng dữ liệu(PDF) 166 Page - Texas Instruments |
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DAC39RF10 bảng dữ liệu(HTML) 166 Page - Texas Instruments |
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166 / 232 page  Table 8-54. EQCNTSZ Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 EQCNTSZ R/W 0h Equalizer counter size: Adjusts how many votes must be accumulated to cause the adaptive equalizer gain to change. Affects all lanes. This is for debug purposes only and the user should generally not need to change this setting. EQCNTSZ : Equalizer Vote Counter Size (votes required to adjust gain) 0 : (default) 511 1 : RESERVED 2 : 1 3 : 3 4 : 7 5 : 15 6 : 31 7 : 63 8 : 127 9 : 255 10-15 : RESERVED 8.52 CDRLOCK Register (Offset = 0238h) [reset = 00h] CDRLOCK is shown in Figure 8-53 and described in Table 8-55. Return to the Register Summary Table. SerDes CDR Lock/Freeze. Figure 8-53. CDRLOCK Register 7 6 5 4 3 2 1 0 RESERVED CDRLOCK R/W-00h R/W-0b Table 8-55. CDRLOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 CDRLOCK R/W 0b When set, the CDR is frozen and no longer tracks. When the CDR is operating in first-order mode, set CDRLOCK to freeze the CDRPHASE value to inspect it. 8.53 CDRPHASE Register (Offset = 0239h) [reset = NA, read-only] CDRPHASE is shown in Figure 8-54 and described in Table 8-56. Return to the Register Summary Table. SerDes CDR Phase Status Figure 8-54. CDRPHASE Register 7 6 5 4 3 2 1 0 CDRPHASE R DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 166 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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