M50LPW040K1T datasheet(15/36 Pages) STMICROELECTRONICS

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M50LPW040

gram/Erase Controller has applied the maximum

number of pulses to the block(s) and still failed to

verify that the block(s) has erased correctly.

Once the Erase Status bit is set to ‘1’ it can only be

reset to ‘0’ by a Clear Status Register command or

a hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail.

Program Status (Bit 4). The Program Status bit

can be used to identify if the memory has applied

the maximum number of program pulses to the

byte and still failed to verify that the byte has pro-

grammed correctly. The Program Status bit should

be read once the Program/Erase Controller Status

bit is ‘1’ (Program/Erase Controller inactive).

When the Program Status bit is ‘0’ the memory has

successfully verified that the byte has pro-

grammed correctly; when the Program Status bit is

‘1’ the Program/Erase Controller has applied the

maximum number of pulses to the byte and still

failed to verify that the byte has programmed cor-

rectly.

Once the Program Status bit is set to ‘1’ it can only

be reset to ‘0’ by a Clear Status Register com-

mand or a hardware reset. If it is set to ‘1’ it should

be reset before a new Program or Erase command

is issued, otherwise the new command will appear

to fail.

VPP Status (Bit 3). The VPP Status bit can be

used to identify an invalid voltage on the VPP pin

during Program and Erase operations. The VPP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if VPP becomes invalid during a Program or

Erase operation.

When the VPP Status bit is ‘0’ the voltage on the

VPP pin was sampled at a valid voltage; when the

VPP Status bit is ‘1’ the VPP pin has a voltage that

is below the VPP Lockout Voltage, VPPLK, the

memory is protected; Program and Erase opera-

tion cannot be performed.

Once the VPP Status bit set to ‘1’ it can only be re-

set to ‘0’ by a Clear Status Register command or a

hardware reset. If it is set to ‘1’ it should be reset

before a new Program or Erase command is is-

sued, otherwise the new command will appear to

fail.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended and is waiting to be re-

sumed. The Program Suspend Status should only

be considered valid when the Program/Erase

Controller Status bit is ‘1’ (Program/Erase Control-

ler inactive); after a Program/Erase Suspend com-

mand is issued the memory may still complete the

operation rather than entering the Suspend mode.

When the Program Suspend Status bit is ‘0’ the

Program/Erase Controller is active or has complet-

ed its operation; when the bit is ‘1’ a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns to

‘0’.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if the Pro-

gram or Block Erase operation has tried to modify

the contents of a protected block. When the Block

Protection Status bit is to ‘0’ no Program or Block

Erase operations have been attempted to protect-

ed blocks since the last Clear Status Register

command or hardware reset; when the Block Pro-

tection Status bit is ‘1’ a Program or Block Erase

operation has been attempted on a protected

block.

Once it is set to ‘1’ the Block Protection Status bit

can only be reset to ‘0’ by a Clear Status Register

command or a hardware reset. If it is set to ‘1’ it

should be reset before a new Program or Block

Erase command is issued, otherwise the new

command will appear to fail.

Using the A/A Mux Interface the Block Protection

Status bit is always ‘0’.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value should be masked.

LOW PIN COUNT (LPC) INTERFACE

CONFIGURATION REGISTERS

When the Low Pin Count Interface is selected sev-

eral additional registers can be accessed. These

registers control the protection status of the Blocks

and read the General Purpose Input pins. See Ta-

ble 14 for an example of the Register Configura-

tion map, valid for the boot memory, i.e. ID0-ID2

floating or driven LOW, VIL and A19-A21 set to ‘1’.

Lock Registers

The Lock Registers control the protection status of

the Blocks. Each Block has its own Lock Register.

Three bits within each Lock Register control the

protection of each block, the Write Lock Bit, the

Read Lock Bit and the Lock Down Bit.

The Lock Registers can be read and written,

though care should be taken when writing as, once

the Lock Down Bit is set, ‘1’, further modifications

to the Lock Register cannot be made until cleared,

to ‘0’, by a reset or power-up.

See Table 15 for details on the bit definitions of the

Lock Registers.

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