M50LPW012K datasheet(2/35 Pages) STMICROELECTRONICS

2 / 35 page

M50LPW012

2/35

Figure 2. Logic Diagram (A/A Mux Interface)

AI06950

DQ0-DQ7

VCC

M50LPW012

VSS

A0-A10

VPP

DESCRIPTION

The M50LPW012 is a 2Mbit (256Kb x8) non-

volatile memory that can be read, erased and

reprogrammed.

These

operations

can

performed using a single low voltage (3.0 to 3.6V)

supply. For fast programming and fast erasing in

production lines an optional 12V power supply can

be used to reduce the programming and the

erasing times.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Blocks can be

protected

individually

prevent

accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are

written to the Command Interface of the memory.

An on-chip Program/Erase Controller simplifies

the process of programming or erasing the

memory by taking care of all of the special

operations that are required to update the memory

contents. The end of a program or erase operation

can

detected

and

any

error

conditions

identified. The command set required to control

the memory is consistent with JEDEC standards.

Two different bus interfaces are supported by the

memory. The primary interface is the Low Pin

Count (or LPC) Standard Interface. This has been

designed to remove the need for the ISA bus in

Figure 3. PLCC Connections

Note: Pins 27 and 28 are not internally connected.

AI06951

LFRAME

ID1

ID0

LAD0

GPI1

TBL

ID3

ID2

GPI0

VSS

VCC

RFU

M50LPW012

IC (VIL)

INIT

RFU

DQ0

VSS

VCC

DQ7

IC (VIH)

A/A Mux

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